With the advent of microprocessors and other electronics that consume more electrical power, comes the need for higher output current power supplies. While microprocessor voltage requirements are decreasing, substantial increases in electric current requirements are offsetting this trend. Future processors may consume current at levels an order of magnitude higher than today's processors, and will dissipate much more power because the operating voltage will not decrease proportionately. GHz class central processing units (CPUs) are routinely specified to draw 30A or more of direct current. Therefore a need has arisen for high current, low voltage power sources which have a small physical size and generate a modest amount of heat. (As is conventional, “power source” or “power supply” refers here to an electrical voltage/current converter, not to the ultimate source of the electricity, such as a battery or generator.)
Furthermore the miniaturization of electronics products has driven the reduction in size of each integrated circuit (IC) or discrete semiconductor such as transistors (e.g., metal-oxide-semiconductor field effect transistors MOSFETs), and increased packing densities of the ICs or FETs on a circuit board. The amount of heat generated per unit area by the reduced footprint (size) ICs or FETs increases with their packing density. The requirements for packaging (housing) these heat-generating ICs or FETs in ever smaller areas, make the need to provide adequate heat exhaust paths, such as thermal heat sinks more urgent, and this is particularly so for high current devices such as power FETs. The packaging requirements for such power FETs and power supplies are demanding, as they must switch high currents in a small physical size.
However, circuit assembly and packaging technology for power supplies have not kept pace with those of ICs. The state-of-the-art packaged power supplies are in the forms of single-in-line package (SIP), dual-in-line package (DIP), small outline package (SO or SOP) and quad flat pack (QFP), which have undesirably large size, high resistance and parasitic capacitance, poor thermal management and high cost. Inside these power supplies, electrical interconnection of the power switching devices such as field effect transistors (FETs) is accomplished with wire bonds onto printed circuit boards. Such wire bonds are prone to resistance, noise, parasitic capacitance and inductance, fatigue and eventual failure. One of the main failure mechanisms is thermal cycling which induces wire bond “lift off”, because of the large thermal expansion coefficient mismatch between the typically aluminum wires and silicon die of the FETs.
The use of printed circuit boards (PCBs) in power supplies also has drawbacks, because the conductive traces on the PCBs are etched, deposited or otherwise attached thin films on the laminated substrate. PCBs using glass filled epoxy resins for the substrate are inexpensive and relatively robust, however cost considerations limit the leads on PCBs to relatively thin films. Most PCBs carry current traces which are no more than 125–150 μm thick. Such thin films cannot carry the high currents required of modern power supplies. Thin conductive leads thereby limit current that can be delivered to or from the FETs, attached to the PCB, without generating excessive amounts of heat.
Therefore a problem remains in high current power supplies, in sourcing and sinking large currents but keeping cost low and limiting temperature rise.